FPGA accelerated DPDK SmartNIC

ready-to-use solution for different applications to offload processing of high-speed network traffic into FPGA accelerator card. It completely remove the risk, uncertainty, and time of FPGA firmware development. Customer creates only software without the need for FPGA know-how and HW development team. Solution provides single standardized API following DPDK standard. It supports packet transfers using our Ultra-Fast FPGA DMA engine with open-source drivers, dynamic software-defined RTE Flow filtering and offload with multiple rule tables, static configuration of traffic processing, dynamic traffic flow management and many more.

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Main features and benefits of solution

No need for RTL or HLS or P4 coding.

You don’t have to code FPGA as fully preconfigured FPGA packet processing pipeline is given and well tested and verified.

Standardized software interface

We provide open-source DPDK software stack to our solution. FPGA packet processing pipeline is controlled by standard RTE Flow interface.

Really high throughput

Solution provides more than 400 Gbps throughput to and from host RAM on given cards and lossless traffic processing at wire-speeds even on the smallest packets at 400G.

Great configurability

Configurable packer parser supporting protocols from L2 to L4 with different filtering options utilizing internal or external memories depending on card peripherals.

Many options

Solution is ready for different link speeds from 100G to 400G and different FPGA accelerator cards from various vendors.

Just don’t care about FPGA design!

Processing pipeline

Provided as a “bitstream” for given FPGA accelerator card.

See some other technical details of FPGA accelerated DPDK SmartNIC solution on XpressSX AGI-FH400G.

brnologic - fpga accelerated dpdk smartnic solution

Interested? Contact us at

support@brnologic.com